|
The CDC 8600 was the last of Seymour Cray's supercomputer designs while working for the Control Data Corporation. As the natural successor to the CDC 6600 and CDC 7600, the 8600 was intended to be about 10 times as fast as the 7600, already the fastest computer on the market. Development started in 1968, shortly after the release of the 7600, but the project soon started to bog down. By 1971 CDC was having cash-flow problems and the design was still not coming together, prompting Cray to leave the company in 1972. The 8600 design effort was eventually cancelled in 1974, and Control Data moved on to the CDC STAR-100 series instead. ==Design== In the 1960s computer design was based on mounting electronic components (transistors, resistors, etc.) on circuit boards. Several boards would be used to make a discrete logic element of the machine, known as a ''module''. Overall machine cycle speed is strongly related to the signal path – the length of the wiring – requiring high-speed computers to make their modules as small as possible. This was at odds with the need to make the modules themselves more complex in order to increase functionality. By the late 1960s the individual components had stopped getting much smaller, so in order to increase the complexity of the machines, the modules would have to grow. In theory, this could slow the machine down due to signalling delays. Cray aimed to solve these contradictory problems by doing both; making each module larger and crammed with many more components, while at the same time making the computer as a whole smaller by packing the modules closer together inside the machine. In the case of the 8600, this led to modules containing eight four-layer circuit boards about 8" by 6", resulting in a stack the size of a large textbook and using up about 3 kilowatts of power. The modules were then packed into a mainframe chassis that was comparatively tiny, a 16-sided cylinder about one meter across and high, sitting on top of a ring of power supplies. With all of this power being dissipated in such a small space, cooling was a major design issue. Cray's refrigeration engineer, Dean Roush, formerly of Amana, placed a sheet of copper inside each of the circuit boards, removing the heat to a copper block on one end where it was cooled by a freon system. This further increased the weight and complexity of the modules, to the point where each one weighed about 15 pounds. The external cooling system was considerably larger than the machine itself. Perhaps unsurprisingly, the 8600 bears a strong resemblance to the later Cray-1.〔("8600 prototype photo" )〕 The components themselves were likewise improved over previous designs. The main CPU circuits moved to ECL-based logic, allowing the clock speed to be increased 125MHz (8ns cycle time) from the 7600's 36.4MHz (27.5ns cycle time) an increase of about four times. Main memory was also moved to an ECL implementation and the machine was equipped with a whopping 256k-words (2 megabytes) standard. The memory was spread across 64 banks, thereby allowing fast access at about 8 ns/word even though the cycle time of any one bank was about 250 ns. A high-speed core memory with a 20 ns access (overall) was also designed as a backup to the semiconductor version. Cray decided that the 8600 would include four complete CPUs sharing the main memory. In order to improve overall throughput, the machine could be operated in a special mode in which a single instruction was sent to all four processors with different data. This technique, today known as SIMD, reduced the total number of memory accesses because the instruction was only read once, instead of four times. Each processor was about 2.5 times as fast as a 7600, so with all four running the machine as a whole would be about 10 times as fast, at about 100 MFLOPS. The 8600 was the first CDC design to move to ASCII-based processing, and therefore used a 64-bit word (eight bytes) instead of the earlier 60-bit word (ten six-bit characters) used on the 6600 and 7600. As in prior designs, instructions were "stuffed" into words, with each instruction taking up either 16- or 32-bits (up from 15/30). The 8600 no longer used the A or B registers as in previous designs, and included a set of 16 general-purpose X registers instead. A 6600/7600 Peripheral Processor system was used for I/O, largely unchanged. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「CDC 8600」の詳細全文を読む スポンサード リンク
|
